The present invention relates generally to the field of electroplating. In particular, the present invention relates to the use of certain acidic electrolytes in electroplating baths.
Electroplating articles with copper coatings is generally well known in the industry. Electroplating methods involve passing a current between two electrodes in a plating solution where one electrode is the article to be plated. A common plating solution would be an acid copper plating solution containing (1) a dissolved copper salt (such as copper sulfate), (2) an acidic electrolyte (such as sulfuric acid) in an amount sufficient to impart conductivity to the bath and (3) additives (such as surfactants, brighteners, levelers and suppressants) to enhance the effectiveness and quality of plating. See generally U.S. Pat. Nos. 5,068,013; 5,174,886; 5,051,154; 3,876,513; and 5,068,013 for a discussion of copper plating baths.
Over time, a number of improvements in electroplating techniques have been made as the articles to be plated evolved in degree of difficulty and standards for plating increased. However, even with such improvements circumstances exist that can lead to plating defects.
Copper plating technology has been particularly important in the manufacture of computer circuit boards. More specifically, during circuit board manufacture, copper electrical connections are provided between various board layers by plating board through holes whereby a thin conductive copper conductive is first applied, typically using electroless copper plating techniques, followed by electroplating copper from acid copper solutions. Copper plating is also employed in circuit board manufacture to plate outer layers where final circuitry is defined. For such applications, panel plating is typically employed, where the full circuit board surface is copper plated followed by photodefining circuitry with a photoresist and then etching in a subtractive process. Alternatively an additive process can be employed, where copper circuits are produced by plating between lines defined by a resist relief image.
More recently, copper plating also has been employed in semiconductor chip manufacture to provide chip interconnections, replacing aluminum conductors. Industry continually demands enhanced performance, including ultra large-scale integration and faster circuits. Consequently, chip interconnects are required at dimensions of 200 nm and less. At such geometries, the resistivity of aluminum (theoretically 2.65xc3x9710xe2x88x928 ohm/meter at room temperature) is considered too high to allow the electronic signal to pass at required speeds. Copper, with a theoretical resistivity of 1.678xc3x9710xe2x88x928 ohm/meter, is a more suitable material to meet the next generation of semiconductor microchips.
Typical processes for defining semiconductor chip interconnects, particularly aluminum interconnects, have involved reactive ion etching of metal layers, e.g. a process that includes metal deposition, photolithographic patterning, line definition through reactive ion etching and dielectric deposition. However, in copper-based systems, reactive ion etching is not practical as a result of the paucity of copper compounds with vapor pressures sufficient to enable removal of the copper as may be desired.
Consequently, alternative strategies have developed, such as the Damascene process. That process starts with deposition of dielectric typically by chemical vapor deposition of silicon materials or organic dielectrics followed by curing, or spin coating silicon materials or organic dielectrics. Patterning by photolithographic processes and reactive ion etching defines the vias and trenches (interconnects) in the dielectric. Barrier layers are then formed by chemical vapor deposition or other methods to isolate the copper lines from the dielectric. Copper is then deposited and excess material removed by chemical or mechanical polishing processes.
Although conventional copper plating systems can be suitable for plating vias and trenches as small as 300 nm with 4:1 aspect ratios, defects such as seams, voids and inclusions can occur with conventional methods when attempting to plate features that are smaller or have higher aspect ratios. Such defects can occur as a result of conformal copper plating, i.e. where all targeted surfaces are plated at the same rate such that the sidewalls of a via or trench plate together forming a seam or a demarcation of disruption where the copper grains are separated and will not anneal to form a continuous copper wire. Defects also will occur at the top rim of a via hole, where electronic charge density can concentrate and result in rapid copper growth that closes off the via before the via is filled sufficiently with metal. Such inadequate metal fill can result in inclusion and voids, disrupting the ability of the plated metal to carry a coherent signal.
A semiconductor wafer is generally plated with excess copper. During the process of manufacturing an integrated circuit, a semiconductor wafer is often polished to remove the excess unwanted materials on the surface of the wafer. Polishing generally takes the form of chemical-mechanical planarization (xe2x80x9cCMPxe2x80x9d) wherein a chemically active slurry is used in conjunction with a polishing pad.
In many conventional electroplating baths numerous organic additives are used, including separate accelerator compounds, separate suppressor compounds and separate leveler compounds. Such organic additives are used to provide certain plating properties, such as good fill of recessed features and low overplating. This is particularly true in copper electroplating baths designed to provide superfill of small apertures during the manufacture of electronic devices, such as integrated circuits.
However, such organic additives can be problematic. A balance must be struck between the use of accelerators, suppressors and levelers to achieve the desired level of copper fill of apertures without void formation. Many factors may affect the stability and consumption of each of the accelerator, suppressor and leveler components in the plating bath. Thus, if one of these components is consumed at a faster rate than the others, the plating characteristics of the bath may change. Alternatively, if one of the organic additives is incorrectly added to the electroplating bath, either during bath make-up or replenishment, the plating characteristics of the bath may not be optimum. Thus, it is desirable to provide or enhance bottom-up fill (superfill) with less reliance on the use of organic additives.
It has been surprisingly found that the use of two or more acids in the electrolyte of an electroplating bath, particularly a copper electroplating bath, results in a metal deposit having good fill of recessed features with reduced overplating as compared to conventional plating baths using one acid for the electrolyte. The use of two or more acids in the electrolyte enhances bottom-up fill in the presence of organic additives and reduces the reliance on such additives. Such improved plating characteristics are particularly suitable for the manufacture of electronic devices where apertures of different sizes are present.
In one aspect, the present invention provides an electroplating bath including a) a source of metal ions; b) an electrolyte including two or more acids; c) and optionally one or more additives.
In a second aspect, the present invention provides a method of depositing a metal layer on a substrate including the steps of: a) contacting a substrate with an electroplating bath including a source of metal ions, an electrolyte including two or more acids, and optionally one or more additives; and b) subjecting the electroplating bath to a current density sufficient to deposit the metal layer.
In a third aspect, the present invention provides a method for manufacturing an electronic device including the steps of: a) contacting the electronic device with an electroplating bath including a source of metal ions, an electrolyte including two or more acids, and optionally one or more additives; and b) subjecting the electroplating bath to a current density sufficient to deposit the metal layer.
The invention also includes articles of manufacture, including electronic packaging devices such as printed circuit boards, multichip modules, semiconductor integrated circuits and the like that contain a copper deposit produced from a plating solution of the invention.
In a fourth aspect, the present invention provides an article of manufacture including an electronic device substrate containing one or more apertures, each aperture containing an electrolytic copper deposit obtained from an electroplating composition that includes at least one soluble copper salt and an electrolyte including two or more acids.
In a fifth aspect, the present invention provides a method for removing excess material from a semiconductor wafer by using a chemical mechanical planarization process which includes contacting the semiconductor wafer with a rotating polishing pad thereby removing the excess material from the semiconductor wafer; wherein the semiconductor wafer has been prior electroplated by a copper electroplating composition including at least one soluble copper salt, and an electrolyte including two or more acids.
In a sixth aspect, the present invention provides a method for removing excess material from a semiconductor wafer by using a chemical mechanical planarization process which includes contacting the semiconductor wafer with a rotating polishing pad thereby removing the excess material from the semiconductor wafer; wherein the semiconductor wafer has been prior electroplated by the composition described above.